This application claims the priority benefit of Taiwan application serial no. 89127632, filed on Dec. 22, 2000.
1. Field of Invention
The present invention relates to a clock trunk architecture. More particularly, the present invention relates to a programmable clock trunk architecture for adjusting clock skew.
2. Description of Related Art
The operation of integrated circuits, for example, central processing units or memories, normally requires the presence of a clock signal. Within an integrated circuit, cells such as flip-flops are either activated by a clock signal, or use a clock signal as a reference in operations. For providing a clock signal to various cells of an integrated circuit, a clock signal generator is often used within the layout of the integrated circuit. In a real world application, the actual lengths of conducting lines from cells of an integrated circuit to the clock signal generator may vary accordingly to the layout of the integrated circuit. Therefore, clock delay and clock skew usually occurs during operations when the clock signal is sent to more than one cell within an integrated circuit.
Between the time it takes for a clock signal to go from the clock signal generator to the cells such as a flip-flop, there might be a time difference, a clock delay, usually caused by the clock buffers and the conducting line between the clock signal generator and the cells. The circuit layout may also cause a clock skew, which represents a time difference between the clock signals actually received at two adjacent cells, even though the clock signals are generated by the same clock signal generator.
Several conventional architectures for transferring clock signals to cells have been used in the designs of circuit layouts, including WASP, trunk-like, divided trunk-like, sub-block, H-tree, and mesh type architectures, which are shown in FIGS. 1A to 1F respectively. For understanding the foregoing architectures, the bold lines represent the trunks of architectures, and arrowheads represent the transfer directions of clock signals in each of the clock trunk architectures.
FIG. 2A is a normalized chart showing the probability of the variation of the clock delay (td) of different architectures shown in FIGS. 1A to 1F. FIG. 2B is also a normalized chart but showing the probability of the variation of the clock skew (tskew) of different architectures shown in FIGS. 1A to 1F. As shown in FIG. 2A, the clock delay of a H-tree type architecture is relatively large and widely spread. According to FIG. 2B, it can be seen that the clock skew of trunk-like architectures is relatively large, and widely spread. The mesh type architecture does not have the problems of the H-tree type and trunk-like architectures, however, its overhead area is large. In the flatten-mode circuit layout, the foregoing architectures are still applicable. In the hierarchy-mode circuit layout, however, neither of the foregoing architectures is able to provide a flexible range for adjusting clock skew, especially on the upper level.
In order to resolve the problems of clock delay, and clock skew, another clock architecture was developed. As shown in FIG. 3A, a clock signal from the clock source 10 is transferred to sub-circuits 20, 22, 24, and 26 through clock buffers 12 and 14, wherein sub-circuits 20 and 22 are connected to clock buffer 12, and sub-circuits 24 and 26 are connected to clock buffer 14. The idea of this clock architecture is to connect sub-circuits having close clock delays to the same clock buffer, so that the clock skew can be reduced by adjusting the driving force on the clock buffer. If the clock delays on sub-circuits 20, 22, 24, and 26 are 3, 4, 1, and 2 respectively, the clock delays and clock skew on all sub-circuits can be effectively reduced by adjusting the driving forces applied on clock buffers 12 and 14 respectively.
However, in such a clock architecture, the flexibility of adjusting clock skew is still limited. As shown in FIG. 3B, it is difficult to reduce the clock skew occurring between sub-circuits 40 and 42 since the difference between the clock delays on sub-circuits 40 and 42 is too large. It is also difficult to reduce the clock skew between cells or sub-circuits that are connected to a clock source across long conducting lines, since the clock delays on those cells or sub-circuits is essentially larger.
In addition, clock skews between cells, especially for those on a circuit of hierarchy mode, cannot be effectively reduced by conventional clock architectures.
Accordingly, one object of the present invention is to provide a programmable clock architecture for reducing the clock delays on cells, as well as the clock skews between cells.
A second object of this invention is to provide a clock architecture capable of efficiently distributing clock signals over cells of circuits in a hierarchy mode, and silicon-on-chip (SOC) circuits.
A third object of this invention is to provide a clock architecture having a greater flexibility for adjusting clock skew.
To achieve these and other advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a clock architecture including a clock source, a trunk, a number of branches, and at least one circuit block. The clock source provides a clock signal. The trunk is connected to the clock source for transferring the clock signal to branches, wherein each branch is connected to the trunk at one end. Each branch transfers a clock signal through at least one clock buffer, wherein each clock buffer is capable of shifting the phase of the clock signal that passes through it. The number of clock buffers located along a branch depends on the required phase shift, therefore, it may vary from branch to branch. The circuit block is connected to all branches through switches, wherein each switch controls the connection between the circuit block and one of branches, and only one switch is on at any one time. The circuit block then receives the clock signal from the branch with an on-state switch.
The switches of the invention can be controlled by programmable switch devices, such as a metal oxide semiconductor transistor switch, I/O pins, ROM code or metal options, so that the on/off state thereof can be controlled in a flexible manner.
In the preferred embodiment of this invention, the clock architecture of the invention includes a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit block. The clock source generates a global clock signal, which is then transferred to the multi-phase clock signal generator connected to the clock source. Upon receipt of a global clock signal, the multi-phase clock signal generator, which is connected to a control bus, generates clock signals of different phases according to the signals from the control bus. Each of the clock signal branches transfers one of the clock signals of different phases, wherein each of the clock signal branches is individually connected to the circuit block through an electrical switch. Only one switch is at an on state at any one time, so that the clock signal of a corresponding phase is transferred to the circuit block.
The switches and control bus of the invention can be controlled by programmable switch devices, such as a metal oxide semiconductor transistor switch, I/O pins, ROM code or metal options, so that the on/off state thereof can be controlled in a flexible manner.
In this invention, the driving forces of the clock buffer connected to the clock source and the clock buffers on the branches are adjustable for reducing clock skew. Alternately, programmable delay buffers can be used for achieving the same goal. Each of the circuit blocks, modules, or IPs can selectively receive a proper clock signal from the selected branch or clock signal line.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.